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TyVis documentation top.

Introduction

TyVis is a VHDL elaboration/simulation support library written in C++. It's intention is to bridge the gap between VHDL semantics, and the discrete event simulation library, warped, on which it depends.

VHDL Constructs

Numeric Types

See UniversalInteger, UniversalReal, and PhysicalLiteral.

Array Types

See Array.

File Types

See FileObject.

Record Types

See Record.

Array Types

See AccessObject.

Signals

See Signal.

Processes

Processes in VHDL are a key concept. Conceptually all processes run concurrently with each other, even during sequential simulation. When a TyVis simulation is run in parallel simulation mode, processes will run concurrently "for real" during simulation.

The TyVis implementation of a process can be found in VHDLProcess.

Elaboration

Simulation

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