VHDLProcess Class Reference

This class implements the LRM definition of a VHDL'93 process. More...

#include <VHDLProcess.hh>

Inheritance diagram for VHDLProcess:

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Collaboration diagram for VHDLProcess:

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List of all members.

Public Member Functions

void vhdlAssertOrReport (bool assertStatement, const RValue &condition, const PhysicalLiteral &timeOccurred, const RValue &message, const RValue &severityLevel, const string &locatorInfo)
 This method executes a VHDL assertion statement.
virtual void executeVHDL ()=0
 This method is an upcall to generated code.
virtual void executeVHDL (VHDLKernel_state &currentState)
 This method is the entry point from VHDLKernel.
void updateSignal (SignalBase *, bool initializingSimulation=false)
void updateSignal (int sigId, VHDLProcess *srcId, VHDLData *data, const ArrayInfo *dInfo, const ArrayInfo *sInfo)
 Resolution functions are not called from updateSignal.
void updateImplicit (SignalBase *, const RValue *)
void updateImplicitAttributes (SignalBase *, const RValue *, bool)
void updateImplicitAttributes (SignalBase *, const RValue *)
void updateDriver (SignalBase *signal, VHDLKernel *srcProcess, int senderSigId, const RValue *newData, ArrayInfo *sourceInfo, ArrayInfo *destInfo)
 The following function updates the driver of the signal.
void updateWait (const VHDLVTime &waitTime)
 Updates the wait state for the current time to "expired" if the wait time has passed.
bool resumeWait (int, const VHDLData &=SAVANT_BOOLEAN_TRUE)
void executeWait (int, const PhysicalLiteral &=SAVANT_INFINITY_TIME)
void setProcedureWait (Wait *myWait)
void disconnectDriver (SignalBase *signal, int processId)
 Disconnects the process specified from the signal specified.
void updateAttribute (Attribute *attribute, const RValue &lastValue=SAVANT_BOOLEAN_FALSE) const
 The second argument is a dummy argument.
void updateDefaultAttributes (SignalBase *signal, const RValue *oldEffVal, bool eventOccurred)
int getWaitLabel ()
EnumerationLiteral locateQuietAttribute (const SignalBase *sig, const VHDLVTime=VHDLVTime::getVHDLVTimeZero()) const
EnumerationLiteral locateEventAttribute (RValue *sig) const
EnumerationLiteral locateStableAttribute (const SignalBase *, const VHDLVTime=VHDLVTime::getVHDLVTimeZero()) const
UniversalIntegerlocateTransactionAttribute (const SignalBase *)
PhysicalLiteral locateLastActiveAttribute (const SignalBase *)
const PhysicalLiteral locateLastEventAttribute (const SignalBase *)
Value locateLastValueAttribute (RValue *signal)
void assignSignal (SignalBase &dest, VHDLKernel *srcId, const RValue &src, const PhysicalLiteral &delay, const PhysicalLiteral &rejTime=SAVANT_ZERO_TIME, const ArrayInfo &dinfo=defaultInfo(), const ArrayInfo &sinfo=defaultInfo())
 Assigns the signal the value of (having the source identifier srcID).Assigns the signal the value of .
void assignSignal (SignalBase &dest, VHDLKernel *srcId, const RValue &src, const VHDLVTime &delay, const VHDLVTime &rejTime=VHDLVTime::getVHDLVTimeZero(), const ArrayInfo &dinfo=defaultInfo(), const ArrayInfo &sinfo=defaultInfo())
 Okay, immaterial of the original type of the signal we are now assiging values to a scalar signal.
virtual void assignNullTransaction (SignalBase &dest, VHDLProcess *srcId, const PhysicalLiteral &delay, const PhysicalLiteral &rejTime=SAVANT_ZERO_TIME, const ArrayInfo &dinfo=defaultInfo(), const ArrayInfo &sinfo=defaultInfo())
 Assigns the signal a null transaction (having the source identifier srcID).Assigns the signal a null transaction.
virtual void assignNullTransaction (SignalBase &dest, VHDLProcess *srcId, const VHDLVTime &delay, const VHDLVTime &rejTime=VHDLVTime::getVHDLVTimeZero(), const ArrayInfo &dinfo=nullInfo(), const ArrayInfo &sinfo=nullInfo())

Protected Member Functions

 VHDLProcess (const string &name, _savant_entity_elab *=NULL)
 Constructor.
 ~VHDLProcess ()
 Destructor.

Private Member Functions

void executeSignalUpdationPhase (Block &scalarSignalsUpdateArray, Block &compositeResolvedSignalsUpdateArray)
 This method does the updating of the input signals.
void vhdlAssertOrReport (bool assertStatement, bool condition, const PhysicalLiteral &timeOccurred, const string &message, const string &severityString, const string &locatorInfo)
 Method used by public version to do the dirty work of assertion handling.
void updateGuard (RValue *)
virtual RValuegetGuard ()
virtual RValuegetGuardExpression ()

Private Attributes

Block scalarSignalsUpdateArray
 The scalar signals updated this simulation cycle.
Block compositeResolvedSignalsUpdateArray
 The composited signals updated this simulation cycle.
EventSigs eventSigs
 array of signal ID's that had events on them this sim cycle.

Detailed Description

This class implements the LRM definition of a VHDL'93 process.

The code defined inside of the method "executeVHDL" represents the sequential code defined by a VHDL process. Some forms of VHDL sequential statements have been defined within this class as a method call.


Constructor & Destructor Documentation

VHDLProcess::VHDLProcess const string &  name,
_savant_entity_elab = NULL
[protected]
 

Constructor.

Parameters:
name - simply passed on to parent class.

VHDLProcess::~VHDLProcess  )  [protected]
 

Destructor.


Member Function Documentation

virtual void VHDLProcess::assignNullTransaction SignalBase dest,
VHDLProcess srcId,
const VHDLVTime delay,
const VHDLVTime rejTime = VHDLVTime::getVHDLVTimeZero(),
const ArrayInfo dinfo = nullInfo(),
const ArrayInfo sinfo = nullInfo()
[virtual]
 

virtual void VHDLProcess::assignNullTransaction SignalBase dest,
VHDLProcess srcId,
const PhysicalLiteral delay,
const PhysicalLiteral rejTime = SAVANT_ZERO_TIME,
const ArrayInfo dinfo = defaultInfo(),
const ArrayInfo sinfo = defaultInfo()
[virtual]
 

Assigns the signal a null transaction (having the source identifier srcID).Assigns the signal a null transaction.

The assigment is done with the delay of . Optionally may the rejection time be assigned. For array assignments can the array information of the source () and the destination () be given.

Each member on the fanout list of the will have an event appended to its private event queue for that signal. This is required for the distributed parallell simulation of Warped.

Parameters:
dest The destination signal.
srcId The source process identifier.
delay The delay before the signal becomes effective.
rejTime The rejection time.
dinfo The destination array info.
sinfo The source array info.

void VHDLProcess::assignSignal SignalBase dest,
VHDLKernel srcId,
const RValue src,
const VHDLVTime delay,
const VHDLVTime rejTime = VHDLVTime::getVHDLVTimeZero(),
const ArrayInfo dinfo = defaultInfo(),
const ArrayInfo sinfo = defaultInfo()
[virtual]
 

Okay, immaterial of the original type of the signal we are now assiging values to a scalar signal.

Note that assigning a value to a signal does not change the value of the signal, but merely generates transactions on the signal. The transactions ultimately get converted to events and get shipped out to the various (VHDL) processes that are sensitive to this signal.

The process of posting transactions on signals also involves a phase called marking. Each scalar signal does its own marking and generates the transactions to be sent out. The actual events are sent out by the process.

Reimplemented from VHDLKernel.

void VHDLProcess::assignSignal SignalBase dest,
VHDLKernel srcId,
const RValue src,
const PhysicalLiteral delay,
const PhysicalLiteral rejTime = SAVANT_ZERO_TIME,
const ArrayInfo dinfo = defaultInfo(),
const ArrayInfo sinfo = defaultInfo()
[virtual]
 

Assigns the signal the value of (having the source identifier srcID).Assigns the signal the value of .

The assigment is done with the delay of . Optionally may the rejection time be assigned. For array assignments can the array information of the source () and the destination () be given.

Each member on the fanout list of the will have an event appended to its private event queue for that signal. This is required for the distributed parallell simulation of Warped.

Parameters:
dest The destination signal.
srcId The source process identifier.
src The source value.
delay The delay before the signal becomes effective.
rejTime The rejection time.
dinfo The destination array info.
sinfo The source array info.

Reimplemented from VHDLKernel.

void VHDLProcess::disconnectDriver SignalBase signal,
int  processId
[virtual]
 

Disconnects the process specified from the signal specified.

Reimplemented from VHDLKernel.

void VHDLProcess::executeSignalUpdationPhase Block scalarSignalsUpdateArray,
Block compositeResolvedSignalsUpdateArray
[private]
 

This method does the updating of the input signals.

virtual void VHDLProcess::executeVHDL VHDLKernel_state currentState  )  [virtual]
 

This method is the entry point from VHDLKernel.

That is, all warped/event related processing happens in VHDLKernel, and then it hands of execution to us through this upcall.

Reimplemented from VHDLKernel.

virtual void VHDLProcess::executeVHDL  )  [pure virtual]
 

This method is an upcall to generated code.

It gets called after the signal updation phase occurs. Therefore, all input signals have been updated, and the code executed in the upcall needs to access these signals and other elements of this process's state, and generate output signal updates.

void VHDLProcess::executeWait int  ,
const PhysicalLiteral = SAVANT_INFINITY_TIME
[virtual]
 

Reimplemented from VHDLKernel.

virtual RValue* VHDLProcess::getGuard  )  [inline, private, virtual]
 

Reimplemented from VHDLKernel.

virtual RValue* VHDLProcess::getGuardExpression  )  [inline, private, virtual]
 

Reimplemented from VHDLKernel.

int VHDLProcess::getWaitLabel  )  [inline, virtual]
 

Reimplemented from VHDLKernel.

EnumerationLiteral VHDLProcess::locateEventAttribute RValue sig  )  const
 

PhysicalLiteral VHDLProcess::locateLastActiveAttribute const SignalBase  ) 
 

Reimplemented from VHDLKernel.

const PhysicalLiteral VHDLProcess::locateLastEventAttribute const SignalBase  ) 
 

Reimplemented from VHDLKernel.

Value VHDLProcess::locateLastValueAttribute RValue signal  ) 
 

EnumerationLiteral VHDLProcess::locateQuietAttribute const SignalBase sig,
const   VHDLVTime = VHDLVTime::getVHDLVTimeZero()
const
 

EnumerationLiteral VHDLProcess::locateStableAttribute const SignalBase ,
const   VHDLVTime = VHDLVTime::getVHDLVTimeZero()
const
 

UniversalInteger* VHDLProcess::locateTransactionAttribute const SignalBase  )  [virtual]
 

Reimplemented from VHDLKernel.

bool VHDLProcess::resumeWait int  ,
const VHDLData = SAVANT_BOOLEAN_TRUE
 

void VHDLProcess::setProcedureWait Wait myWait  )  [inline, virtual]
 

Reimplemented from VHDLKernel.

void VHDLProcess::updateAttribute Attribute attribute,
const RValue lastValue = SAVANT_BOOLEAN_FALSE
const
 

The second argument is a dummy argument.

void VHDLProcess::updateDefaultAttributes SignalBase signal,
const RValue oldEffVal,
bool  eventOccurred
 

void VHDLProcess::updateDriver SignalBase signal,
VHDLKernel srcProcess,
int  senderSigId,
const RValue newData,
ArrayInfo sourceInfo,
ArrayInfo destInfo
[virtual]
 

The following function updates the driver of the signal.

Implements VHDLKernel.

void VHDLProcess::updateGuard RValue  )  [private, virtual]
 

Reimplemented from VHDLKernel.

void VHDLProcess::updateImplicit SignalBase ,
const RValue
 

void VHDLProcess::updateImplicitAttributes SignalBase ,
const RValue
 

void VHDLProcess::updateImplicitAttributes SignalBase ,
const RValue ,
bool 
 

void VHDLProcess::updateSignal int  sigId,
VHDLProcess srcId,
VHDLData data,
const ArrayInfo dInfo,
const ArrayInfo sInfo
 

Resolution functions are not called from updateSignal.

The driver which modifies the value of the signal has the responsibility to update the values of all the fanouts of the signals and send the corresponding messages to them. This is done to avoid multiple resolution function computation. If the destination were to resolve its signals, the same values will be computed by each of the fanouts. This is why the check of resolved funciton has been removed from updateSignal.

void VHDLProcess::updateSignal SignalBase ,
bool  initializingSimulation = false
[virtual]
 

See also:
VHDLKernel::updateSignal

Reimplemented from VHDLKernel.

void VHDLProcess::updateWait const VHDLVTime waitTime  )  [virtual]
 

Updates the wait state for the current time to "expired" if the wait time has passed.

Reimplemented from VHDLKernel.

void VHDLProcess::vhdlAssertOrReport bool  assertStatement,
bool  condition,
const PhysicalLiteral timeOccurred,
const string &  message,
const string &  severityString,
const string &  locatorInfo
[private]
 

Method used by public version to do the dirty work of assertion handling.

void VHDLProcess::vhdlAssertOrReport bool  assertStatement,
const RValue condition,
const PhysicalLiteral timeOccurred,
const RValue message,
const RValue severityLevel,
const string &  locatorInfo
 

This method executes a VHDL assertion statement.

Parameters:
assertStatement "true" if this is an assert statement, "false" if it's a report statement. Merely changes formatting of output slightly.
condition This is the expression that the assertion "trips" on. If it's true, the assertion trips, false it doesn't. For report statments, you must always pass "true".
message The message that this statement will print when it trips.
severityString Will be reported as the severity of the violation.
locatorInfo Will be reported as where the error occurred.


Member Data Documentation

Block VHDLProcess::compositeResolvedSignalsUpdateArray [private]
 

The composited signals updated this simulation cycle.

EventSigs VHDLProcess::eventSigs [private]
 

array of signal ID's that had events on them this sim cycle.

Used for wait resumption.

Block VHDLProcess::scalarSignalsUpdateArray [private]
 

The scalar signals updated this simulation cycle.


The documentation for this class was generated from the following file:
Generated on Fri Mar 31 11:18:36 2006 for Tyvis by  doxygen 1.4.6