Subject: bug: the simulation is sticked out
dmsidorov@mtu-net.ru
Date: Mon Mar 26 2001 - 12:00:08 MST
Hello!
I have found that the next code can be parsed without any warnings but
but compiled simulation will have been sticked out at the stage of
data initialisaton.
--------CUT HERE -------------
entity ts6 is
end ts6;
architecture behav of ts6 is
signal CK : bit := '0';
begin
cnt : process
begin
CK <= not CK after 10 us;
end process;
end behav;
--------CUT HERE -------------
But if the
CK <= not CK after 10 us;
will be replaced with
CK <= not CK;
wait for 10 us;
than it can be simulated without any of trouble.
I am use savant 1.02.1 (Nov 6, 1999) and tyvis 1.02.
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