Subject: Re: bug: the simulation is sticked out
From: Dhananjai Madhava Rao (dmadhava@ECECS.UC.EDU)
Date: Tue Mar 27 2001 - 07:31:05 MST
Hi,
Thanks for the bug report. I will take a look at the problem soon.
with regards
-DJ
On Mon, 26 Mar 2001 dmsidorov@mtu-net.ru wrote:
> Hello!
>
> I have found that the next code can be parsed without any warnings but
> but compiled simulation will have been sticked out at the stage of
> data initialisaton.
>
> --------CUT HERE -------------
> entity ts6 is
> end ts6;
> architecture behav of ts6 is
> signal CK : bit := '0';
> begin
> cnt : process
> begin
> CK <= not CK after 10 us;
> end process;
> end behav;
> --------CUT HERE -------------
>
> But if the
> CK <= not CK after 10 us;
> will be replaced with
> CK <= not CK;
> wait for 10 us;
> than it can be simulated without any of trouble.
>
> I am use savant 1.02.1 (Nov 6, 1999) and tyvis 1.02.
>
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