Subject: Re: 'EVENT attribute. (fwd)
From: Dhananjai Madhava Rao (dmadhava@ECECS.UC.EDU)
Date: Sun Apr 22 2001 - 12:45:57 MDT
Hi,
> Thank you for eplanation. Yes, the signal ck unlike variable
> will have been really changed at the next delta cycle,
> that will have been skiped.
> But you example of solution
>
> > There are several ways you could modify your source. I tried doing this
> > one, and it worked:
> >
> > ck <= not ck after 1 us;
> >
> > hope this helped.
>
> is very simile with example that had ran out of memory and sticked down
> in my machine. I have attached it here.
> I am use savant 1.02.1 (Nov 6, 1999) and tyvis 1.02 on Debian GNU/Linux 2.2
> kernel version 2.2.17 with gcc 2.95.2 and glibc 2.1.3.
>
> Will the next example be worked on your machine? Please, do not forget
> to set ulimit -v , it may be dangerous in Linux kernel 2.2.x!
>
Your example had a syntax error and a semantic error.
1. the type of the signal "CK" was missing in the signal definition.
2. The "exit" statement is valid only with loops (for, while etc.) It has
no effect when used out side loops (is this a semantic error? and
should the analyzer be catching it?). Because of this, your example
had this problem:
process "clock" would never return control because there were
not wait (or equivalent) statements. It would continously
generate signal assignments (or transtactions/events) which
never get processed. But these transactions take up memory.
So eventually the simulation will run out of memory!
You need to rewrite process "clock" so that is semantically valid (as per
your definition/requirements/specifications). I am not a VHDL programmer.
Consequently, I cannot be of much help to rewrite your VHDL program.
Maybe some of the VHDL developers in this mailing list can be of better
help to you?
thanks
with regards
-DJ
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