Subject: About TyVIS
From: TunLee (tunlee@sina.com)
Date: Wed Jun 13 2001 - 21:42:05 MDT
Hi, Sir
I developed a Parallel Verilog Simulation Template Package based on WARPED, and write the package similar to the TyVIS package. But when write program to test my package, it reports error in link phase, so I changed the Makefile to build the program and auto rebuild the WARPED and my package, it also reprot error in link phase. I have exampled the TyVIS package and checked my code, and cannot find why these happened.
I think that to write parallel simulation package like TyVIS based on WARPED, I have to write My on TimeWarp objects, for example, in my package is VerilogKernel and VerilogKernel_state classes, I altered your VHDLKernel and VHDLKernel_state to meet my need, and delete some member data and member functions, Is this the key which report the error? Can you give me detailed explanation on how to write
package like TyVIS? or if your want to get more understand my problem, can I send you the VerilogKernel and VerilogKernel_state files? Thank you!
--With Regard
--TunLee
tunlee@sina.com
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