Subject: Re: About TyVIS
From: Dale E Martin (dmartin@clifton-labs.com)
Date: Thu Jun 14 2001 - 08:16:52 MDT
> I developed a Parallel Verilog Simulation Template Package based on
> WARPED, and write the package similar to the TyVIS package.
That sounds very neat - what are you using for a Verilog front end? Are
you on the geda-dev mailing list? There are Verilog projects discussed
there as well as other free EDA tool projects.
> But when write program to test my package, it reports error in link
> phase, so I changed the Makefile to build the program and auto rebuild
> the WARPED and my package, it also reprot error in link phase. I have
> exampled the TyVIS package and checked my code, and cannot find why these
> happened.
Well, in general link errors can be hard to find and _very_ hard to
diagnose remotely. What platform and tools are you using? If you're using
GNU tools on some platform, then I suggest that you'll want to use
"c++filt" and "nm" to try to debug your problem. "c++filt" will demangle
the method names that the linker is complaining about. "nm" can inspect a
.o file or a .a file and tell you what functions/methods are defined in an
object file.
So basically, you want to use "c++filt" to find the missing function, and
then you want to go look at the appropriate .o file and see if they are
listed as being undefined there. If it's undefined in the .o file, then
you've declared the method but haven't defined it. That generally happens
to me by making a "scope" mistake - basically forgetting to make a method
part of a class and putting it into global scope, or some error like that.
If the method is defined, then at link phase you're missing that object
file from the link. It's not getting put into your .a file, you're not
linking the .a file, or some similar problem to that.
Other problems can be much stranger - compiler specific things like missing
vtables or things like that.
> I think that to write parallel simulation package like TyVIS based on
> WARPED, I have to write My on TimeWarp objects, for example, in my
> package is VerilogKernel and VerilogKernel_state classes, I altered your
> VHDLKernel and VHDLKernel_state to meet my need, and delete some member
> data and member functions, Is this the key which report the error? Can
> you give me detailed explanation on how to write package like TyVIS? or
> if your want to get more understand my problem, can I send you the
> VerilogKernel and VerilogKernel_state files? Thank you!
Supply a little more information, like the error messages you're actually
seeing, and maybe we can help you a little.
Thanks,
Dale
-- Dale E. Martin, Clifton Labs, Inc. Senior Computer Engineer dmartin@cliftonlabs.com http://www.cliftonlabs.com pgp key available
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