Simulation Questions/two-entity test

Subject: Simulation Questions/two-entity test
From: Dreja Novak (adreja@yahoo.com)
Date: Tue Jul 31 2001 - 23:20:43 MDT

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Hello,

First of all thanks for writing Savant/TyVis/Warped
package!

I successfully installed all three packages on my
Debian system where for Savant I used deb package
and the other two built from the source.

I successfully run the test provided in the
SimulationGuide paper but as soon I added an
entity it seems not to work. A little modifyed
source of the one provided in the SimulationGuide
is attached below.
What is the problem that the line:

  tvec(1) <= not tvec(0);

works and by using an entity test of input a and
output b and the same behav.:

  b <= not a;

does not work. Where I did mistake?

Thank you very much for your help,
Uros

BTW1: Please send group reply as I am not on the list.

BTW2: Is the only way to view simulational data
  through usage of commands as write from standard
  package? If is there already a package written to
  support VCD or any other standard output file?

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library ieee;
use ieee.std_logic_1164.all;

entity test is
  port (
    a: in std_logic;
    b: out std_logic
  );
end test;

architecture behav of test is
begin
  b <= not(a);
end behav;

library ieee;
use ieee.std_logic_1164.all;

library std;
use std.textio.all;

entity myEntity is
  -- empty entity
end myEntity;

architecture behav of myEntity is

component test
  port (
    a: in std_logic;
    b: out std_logic
  );
end component;

  signal tvec: std_logic_vector(0 to 1) := ('0','0');

begin
  uut: test port map(a=>tvec(0),b=>tvec(1));
  --tvec(1) <= not tvec(0);
  
  myProcess: process is
      
    variable traceLine: LINE;
    variable space: string(1 to 2) := " ";
    
    file RESULT_FILE: text open WRITE_MODE is "results.out";
    
  begin
    wait for 20 ns;
  
    write(traceLine, To_bitvector(tvec));
    write(traceLine, space);
    
    tvec(0) <= transport '1';
      
    wait for 20 ns;
      
    write(traceLine, To_bitvector(tvec));
    write(traceLine, space);

    tvec(0) <= transport '0';
      
    wait for 20 ns;
      
    write(traceLine, To_bitvector(tvec));
    write(traceLine, space);
    writeLine(RESULT_FILE, traceLine);
      
    wait;
      
  end process myProcess;
end behav;

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