Subject: problem with generate statement
From: Tuukka Toivonen (tuukkat@ees2.oulu.fi)
Date: Wed Oct 17 2001 - 06:07:09 MDT
I've been using Savant and learning VHDL for a while, but now
there's something I don't understand. I have a generate-statement
in my VHDL, but it causes an "xxxx undeclared" error when
compiling after publishing with scram. Anyone know what's the problem?
c_elab.cc: In method `void
SGwork_Ddim1neg24_work_Ddim1neg24_Dstruc_ALBL_0x84714e0Awork_Ddim1neg24_Dstruc_elab::createNetInfo()':
SGwork_Ddim1neg24_work_Ddim1neg24_Dstruc_ALBL_0x84714e0Awork_Ddim1neg24_Dstruc_elab.cc:50:
`ALBL_0x84714e0Awork_Ddim1neg24_Dstruc_Oa' undeclared (first use this
function)
SGwork_Ddim1neg24_work_Ddim1neg24_Dstruc_ALBL_0x84714e0Awork_Ddim1neg24_Dstruc_elab.cc:50:
(Each undeclared identifier is reported only once
SGwork_Ddim1neg24_work_Ddim1neg24_Dstruc_ALBL_0x84714e0Awork_Ddim1neg24_Dstruc_elab.cc:50:
for each function it appears in.)
make: ***
[SGwork_Ddim1neg24_work_Ddim1neg24_Dstruc_ALBL_0x84714e0Awork_Ddim1neg24_Dstruc_elab.o]
Error 1
s-inf-pc24 ~/work/vhdl> gcc --version
egcs-2.91.66
entity dim1neg24 is port(
X: in bit_vector(0 to 4);
Y: out bit_vector(0 to 4));
end;
architecture struc of dim1neg24 is
begin
Y(4) <= X(4);
for a in 0 to 3 generate
Y(a) <= X(a) nor X(4);
end generate;
end;
entity myentity is
end;
architecture struc of myentity is
component dim1neg24 is port(
X: in bit_vector(0 to 4);
Y: out bit_vector(0 to 24));
end component;
for all: dim1neg24 use entity WORK.dim1neg24(struc);
signal A,R : bit_vector(0 to 4);
begin
A <= "00000";
neg: dim1neg24 port map(A,R);
process (R)
begin
report "reporting";
end process;
end;
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