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library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
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entity AcsAcqShiftReg_tb is

end AcsAcqShiftReg_tb;

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architecture sa of AcsAcqShiftReg_tb is

  component AcsAcqShiftReg
    port (
      GCLKxC         : in  std_logic;
      ShiftOutxD     : out std_logic;
      Sector0CountxD : in  std_logic_vector(23 downto 0);
      Sector1CountxD : in  std_logic_vector(23 downto 0);
      Sector2CountxD : in  std_logic_vector(23 downto 0);
      Sector3CountxD : in  std_logic_vector(23 downto 0);
      CountScalexD   : in  std_logic_vector(23 downto 0);
      AnalogScalexD  : in  std_logic_vector(15 downto 0);
      Lin0xD         : in  std_logic_vector(3 downto 1);
      Lin1xD         : in  std_logic_vector(3 downto 0);
      Lin2xD         : in  std_logic_vector(3 downto 0);
      Lin3xD         : in  std_logic_vector(3 downto 0);
      ErrComDownxD   : in  std_logic_vector(7 downto 0);
      ShiftEnxS      : in  std_logic;
      LoadEnxS       : in  std_logic);
  end component;

  signal GCLKxC         : std_logic;
  signal ShiftOutxD     : std_logic;
  signal Sector0CountxD : std_logic_vector(23 downto 0);
  signal Sector1CountxD : std_logic_vector(23 downto 0);
  signal Sector2CountxD : std_logic_vector(23 downto 0);
  signal Sector3CountxD : std_logic_vector(23 downto 0);
  signal CountScalexD   : std_logic_vector(23 downto 0);
  signal AnalogScalexD  : std_logic_vector(15 downto 0);
  signal Lin0xD         : std_logic_vector(3 downto 1);
  signal Lin1xD         : std_logic_vector(3 downto 0);
  signal Lin2xD         : std_logic_vector(3 downto 0);
  signal Lin3xD         : std_logic_vector(3 downto 0);
  signal ErrComDownxD   : std_logic_vector(7 downto 0);
  signal ShiftEnxS      : std_logic;
  signal LoadEnxS       : std_logic;
  signal reset : std_logic;
  
begin  -- sa

  DUT: AcsAcqShiftReg
    port map (
      GCLKxC         => GCLKxC,
      ShiftOutxD     => ShiftOutxD,
      Sector0CountxD => Sector0CountxD,
      Sector1CountxD => Sector1CountxD,
      Sector2CountxD => Sector2CountxD,
      Sector3CountxD => Sector3CountxD,
      CountScalexD   => CountScalexD,
      AnalogScalexD  => AnalogScalexD,
      Lin0xD         => Lin0xD,
      Lin1xD         => Lin1xD,
      Lin2xD         => Lin2xD,
      Lin3xD         => Lin3xD,
      ErrComDownxD   => ErrComDownxD,
      ShiftEnxS      => ShiftEnxS,
      LoadEnxS       => LoadEnxS);

   Sector0CountxD <= X"AAAAAA";
   Sector1CountxD <= X"BBBBBB";
   Sector2CountxD <= X"CCCCCC";
   Sector3CountxD <= X"DDDDDD";
   CountScalexD   <= X"EEEEEE"; 
   AnalogScalexD  <= X"FFFF";
   Lin0xD        <= "000";
   Lin1xD        <= "1010";
   Lin2xD        <= "1111";
   Lin3xD        <= "0101";
   ErrComDownxD  <= X"AA";
  
  process 
    variable i : integer;
  begin  -- process
    GCLKxC <= '0';
    for i in 0 to 1000 loop
      wait on GCLKxC;
      GCLKxC <= not GCLKxC after 25 ns;
    end loop;  -- i
    wait;
  end process;

  reset <= '0', '1' after 10 ns;
  
  process
   begin  -- process
     ShiftEnxS <='0';
     LoadEnxS <= '0';
     wait until rising_edge(GCLKxC);
     wait until rising_edge(GCLKxC);
     wait until rising_edge(GCLKxC);
     LoadEnxS <='1';
     wait until rising_edge(GCLKxC);
     LoadEnxS <= '0';
     ShiftEnxS <='1';
     wait;
 end process; 

 process (GCLKxC, reset)
     variable traceLine : LINE;
     variable space : string(1 to 2) := "  ";
     constant header : string(1 to 16) := FF & "      Time  out" ;
     file RESULT_FILE: text open WRITE_MODE is "results.out";

 begin  -- process
     if reset = '0' then                -- asynchronous reset (active low)
       write (traceline,header);
       writeLine(RESULT_FILE,traceline);
       writeLine(RESULT_FILE,traceline);       
     elsif GCLKxC'event and GCLKxC = '1' then  -- rising clock edge
       write(traceline,now,justified=> right,field=>10,unit => ns);
       write(traceline,To_bit(ShiftOutxD),justified=> right,field=>5);
       writeLine(RESULT_FILE,traceline);
     end if;
   end process;  

 end sa;