[savant-devel] compiling vhdl code problem

[Eric Carlson]

Hello,

I have this VHDL file that will publish-cc with Savant but gives errors
when I try to compile it:


work_myand_behavior_elab.hh: No such file or directory
make: *** [work_myand_behavior.o] Error 1


I was wondering if someone could tell me whether the cause of the
problem is with my VHDL code or with Savant.


Thanks,


Eric Carlson
-------------- next part --------------
--This should be a shift register with a test bench.
--Savant parses and makes the cc files, but we get
--compiler errors when trying to "make" the files:
--work_myand_behavior_elab.hh: No such file or directory
--make: *** [work_myand_behavior.o] Error 1



---------------------------------------------------

entity shift_reg is
port(	I:		in bit;
	clock:		in bit;
	shift:		in bit;
	Q:		out bit
);
end shift_reg;

---------------------------------------------------

architecture behv of shift_reg is

    -- initialize the declared signal
    signal S: bit_vector(2 downto 0):="111";

begin
    
    process(I, clock, shift, S)
    begin

	-- everything happens upon the clock changing
	if clock'event and clock='1' then
	    if shift = '1' then
		S <= I & S(2 downto 1);
	    end if;
	end if;

    end process;
	
    -- concurrent assignment
    Q <= S(0);

end behv;

----------------------------------------------------



entity shifter_TB is			-- entity declaration
end shifter_TB;

architecture TB of shifter_TB is

    component shift_reg
    port(   I:	in bit;
	    clock:	in bit;
	    shift:	in bit;
	    Q:	out bit
    );
    end component;

    signal T_I:		bit;
    signal T_clock:	bit;
    signal T_shift:	bit;
    signal T_Q:		bit;

begin

    U_shifter: shift_reg port map (T_I, T_clock, T_shift, T_Q);
	
    -- concurrent process of clock
    process
    begin
	T_clock <= '0';
	wait for 5 ns;
	T_clock <= '1';
	wait for 5 ns;
    end process;

    -- concurrent process of test	
    process

	variable err_cnt: integer := 0;

    begin								
	T_shift <= '1';			-- start shifting  
	T_I <= '0';
	wait for 20 ns;
	T_I <= '1';	 		-- 1st/2nd bit input
	wait for 20 ns;
	T_I <= '0';			-- 3rd bit input
	wait for 10 ns;
	T_I <= '1';			-- 4th bit input
	wait;
    end process;
	
    process

	variable err_cnt: integer :=0; 

    begin
	
	-- case 1
	wait for 30 ns;
	assert(T_Q='0') report "Test1 Failed !"
	severity error;			 
	if (T_Q/='0') then
	    err_cnt:=err_cnt+1;
	end if;
		
	-- case 2
	wait for 10 ns;
	assert(T_Q='0') report "Test2 Failed !"
	severity error;
	if (T_Q/='0') then
	    err_cnt:=err_cnt+1;
	end if;
		
	-- case 3
	wait for 10 ns;
	assert(T_Q='1') report "Test3 Failed !"
	severity error;
	if (T_Q/='1') then
	    err_cnt:=err_cnt+1;
	end if;
		
	-- case 4
	wait for 10 ns;
	assert(T_Q='1') report "Test4 Failed !"
	severity error;
	if (T_Q/='1') then
	    err_cnt:=err_cnt+1;
	end if;
		
	-- summary of all the tests
	if (err_cnt=0) then 
	    assert (false) 
	    report "Testbench of Shifter completed successfully!"
	    severity note;
	else
	    assert (true)
	    report "Something wrong, try again!"
	    severity error;
	end if;
			
	wait;

    end process;

end TB;

----------------------------------------------------------------
configuration CFG_TB of shifter_TB is
	for TB
	end for;
end CFG_TB;
-----------------------------------------------------------------