VHDL Tools (SAVANT/TyVIS/warped/VESTs)

VHDL Tools

Clifton Labs maintains a set of open source tools for VHDL analysis and simulation. The tools include:

SAVANT is a VHDL analyzer that parses and type-checks VHDL models and converts them to a the IIR object model of the AIRE standard (gzip'ed copy).
TyVIS: is a code-generator and VHDL simulation kernel that bridges the IIR object model and the warped simulation kernel API.
warped is a general purpose discrete event simulation kernel.
VESTs is a VHDL test suite.
Bug Tracking for all these tools has been been setup using the open source bugzilla software system. You can browse the reported bugs or post new bugs regarding these VHDL tools using this link.
Mailing Lists for all of these tools are maintained. In general each tool has two mailing lists suffixed by either "-devel" for developers or "-users" for users. These are subscription based mailing lists and are relatively low traffic.